1. Field of the Invention
The present invention relates to a layout method, and particularly relates to a mask pattern correction method.
2. Description of Related Art
As the integration of circuits continues to increase, the dimensions of circuit devices are developed to be miniaturized. Photolithography is an essential and critical step in the fabricating process of semiconductor devices. In metal-oxide-semiconductor (MOS) devices, for instance, structural elements, such as patterns of various layers and regions with dopants, are all defined by a photolithographic process.
Whether the device integration of semiconductor technology can advance to smaller critical dimensions (CD) is dependent upon the development of photolithographic technology. To meet such a requirement, methods for enhancing mask resolution, such as optical proximity correction (OPC) and phase shift mask (PSM), have been developed.
The objective of OPC is to eliminate the shift of critical dimension (CD) caused by proximity effect. The proximity effect refers to the enlargement of a light caused by diffraction when the light passes through a mask to form patterns on a chip. In addition, the light is reflected through a semiconductor substrate and a photoresist layer on the surface of the chip, which results in interference. Hence, the actual exposure dose of the photoresist layer is changed for repeated exposure. Such an effect becomes even more obvious when the critical dimensions are reduced, especially when the critical dimensions are close to the wavelength of the light.
Therefore, the conventional optical proximity correction is applied in improving the form of the opening patterns. However, during a correction process such as optical proximity correction, not all the openings can be corrected to a tolerable range of critical dimension bias value on each axis in one time of correction. When the bias value on the x axis is acceptable, the bias value on the y axis may not be tolerable. When the opening patterns are corrected to adjust the bias value on the y axis, the bias value on the x axis may exceed the tolerable range due to such a correction. Therefore, during the layout of the mask patterns, it usually requires a lot of time to repeatedly adjust each device pattern in the correction process.